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1

[Frontiers in Electronic Testing] Timing Performance of Nanometer Digital Circuits Under Process Variations Volume 39 || Designing with FinFETs and Process Variation Impact

Champac, Victor, Garcia Gervacio, Jose

Year:

2018

Language:

english

File:

PDF, 1.45 MB

english, 2018

2

[IEEE 2008 IEEE International Symposium on Circuits and Systems - ISCAS 2008 - Seattle, WA, USA (2008.05.18-2008.05.21)] 2008 IEEE International Symposium on Circuits and Systems - A design methodology for logic paths tolerant to local intra-die variations

Iparraguirre-Cardenas, Daniel, Garcia-Gervacio, Jose L., Champac, Victor

Year:

2008

Language:

english

File:

PDF, 198 KB

english, 2008

3

Early Selection of Critical Paths for Reliable NBTI Aging-Delay Monitoring

Gomez, Andres F., Champac, Victor

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2016

Language:

english

File:

PDF, 2.71 MB

english, 2016

4

Resistive bridge defect detection enhancement under parameter variations combining Low VDD and body bias in a delay based test

Hector Villacorta, Victor Champac, Sebastià Bota, Jaume Segura

Journal:

Microelectronics Reliability

Year:

2012

Language:

english

File:

PDF, 858 KB

english, 2012

5

Screening small-delay defects using inter-path correlation to reduce reliability risk

García-Gervacio, José L., Nocua, Alejandro, Champac, Victor

Journal:

Microelectronics Reliability

Year:

2015

Language:

english

File:

PDF, 1.51 MB

english, 2015

6

Testing of Stuck-Open Faults in Nanometer Technologies

Champac, Victor, Vazquez Hernandez, Julio, Barcelo, Salvador, Gomez, Roberto, Hawkins, Chuck, Segura, Jaume

Journal:

IEEE Design & Test of Computers

Year:

2012

Language:

english

File:

PDF, 1003 KB

english, 2012

7

Gate Sizing Methodology with a Novel Accurate Metric to Improve Circuit Timing Performance under Process Variations

Perez-Rivera, Zahira, Tlelo-Cuautle, Esteban, Champac, Victor

Journal:

Year:

2020

File:

PDF, 1.08 MB

2020

8

An Efficient Metric-Guided Gate Sizing Methodology for Guardband Reduction Under Process Variations and Aging Effects

Gomez, Andres, Champac, Victor

Journal:

Journal of Electronic Testing

Year:

2019

File:

PDF, 1.48 MB

2019

9

[IEEE 2019 IEEE Latin American Test Symposium (LATS) - Santiago, Chile (2019.3.11-2019.3.13)] 2019 IEEE Latin American Test Symposium (LATS) - A Semi-analytical Model for Interconnect Open Defects in FinFET Logic Cells

Forero, Freddy, Galliere, Jean-Marc, Renovell, Michel, Champac, Victor

Year:

2019

Language:

english

File:

PDF, 826 KB

english, 2019

10

IDDQ Testing of Opens in CMOS SRAMs

Victor H. Champac, José Castillejos, Joan Figueras

Journal:

Journal of Electronic Testing

Year:

1999

Language:

english

File:

PDF, 79 KB

english, 1999

11

[IEEE 2014 IEEE 32nd VLSI Test Symposium (VTS) - Napa, CA, USA (2014.04.13-2014.04.17)] 2014 IEEE 32nd VLSI Test Symposium (VTS) - Hot topic session 12B: Stay relevant with standards-based DFT

Clark, C J, Champac, Victor

Year:

2014

Language:

english

File:

PDF, 107 KB

english, 2014

12

[IEEE 2009 52nd IEEE International Midwest Symposium on Circuits and Systems (MWSCAS) - Cancun, Mexico (2009.08.2-2009.08.5)] 2009 52nd IEEE International Midwest Symposium on Circuits and Systems - A methodology to compute the statistical fault coverage of small delays due to opens

Garcia-Gervacio, Jose L., Champac, Victor

Year:

2009

Language:

english

File:

PDF, 575 KB

english, 2009

13

[IEEE 2016 17th Latin-American Test Symposium (LATS) - Foz do Iguacu, Brazil (2016.4.6-2016.4.8)] 2016 17th Latin-American Test Symposium (LATS) - A methodology for NBTI circuit reliability at reduced power consumption using dual supply voltage

Forero, Freddy, Gomez, Andres, Champac, Victor

Year:

2016

Language:

english

File:

PDF, 2.49 MB

english, 2016

14

CGTDEMO --- educational software for the central limit theorem

Jovanovic-Dolecek, Gordana, Champac, Victor H.

Journal:

ACM SIGCSE Bulletin

Year:

2000

Language:

english

File:

PDF, 288 KB

english, 2000

15

[IEEE 2015 16th Latin-American Test Symposium (LATS) - Puerto Vallarta, Mexico (2015.3.25-2015.3.27)] 2015 16th Latin-American Test Symposium (LATS) - Impact of increasing the fin height on soft error rate and static noise margin in a FinFET-based SRAM cell

Villacorta, Hector, Gomez, Roberto, Bota, Sebastia, Segura, Jaume, Champac, Victor

Year:

2015

Language:

english

File:

PDF, 1.34 MB

english, 2015

16

[IEEE 2018 IEEE 19th Latin-American Test Symposium (LATS) - Sao Paulo, Brazil (2018.3.12-2018.3.14)] 2018 IEEE 19th Latin-American Test Symposium (LATS) - A metric-guided gate-sizing methodology for aging guardband reduction

Gomez, Andres F., Gomez, Roberto, Champac, Victor

Year:

2018

Language:

english

File:

PDF, 901 KB

english, 2018

17

[IEEE 2008 IEEE Computer Society Annual Symposium on VLSI - Montpellier, France (2008.04.7-2008.04.9)] 2008 IEEE Computer Society Annual Symposium on VLSI - Testing Skew and Logic Faults in SoC Interconnects

Hernández, Néstor, Champac, Victor

Year:

2008

Language:

english

File:

PDF, 1.53 MB

english, 2008

18

Impact of Fin-Height on SRAM Soft Error Sensitivity and Cell Stability

Villacorta, Hector, Segura, Jaume, Champac, Victor

Journal:

Journal of Electronic Testing

Year:

2016

Language:

english

File:

PDF, 958 KB

english, 2016

19

Modeling and Detectability of Full Open Gate Defects in FinFET Technology

Forero, Freddy, Villacorta, Hector, Renovell, Michel, Champac, Victor

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2019

Language:

english

File:

PDF, 45 KB

english, 2019

20

Guest Editorial

Fabian Vargas, Victor Champac

Journal:

Journal of Electronic Testing

Year:

2004

Language:

english

File:

PDF, 29 KB

english, 2004

21

[IEEE 2011 IEEE VLSI Test Symposium (VTS) - Dana Point, CA, USA (2011.05.1-2011.05.5)] 29th VLSI Test Symposium - A new methodology for realistic open defect detection probability evaluation under process variations

Moreno, Jesus, Champac, Victor, Renovell, Michel

Year:

2011

Language:

english

File:

PDF, 754 KB

english, 2011

22

[IEEE 2012 13th Latin American Test Workshop - LATW - Quito, Ecuador (2012.04.10-2012.04.13)] 2012 13th Latin American Test Workshop (LATW) - Low voltage testing for interconnect opens under process variations

Moreno, Jesus, Champac, Victor, Renovell, Michel

Year:

2012

Language:

english

File:

PDF, 1.10 MB

english, 2012

23

[IEEE 2009 27th IEEE VLSI Test Symposium (VTS) - Santa Cruz, CA, USA (2009.05.3-2009.05.7)] 2009 27th IEEE VLSI Test Symposium - Stuck-Open Fault Leakage and Testing in Nanometer Technologies

Vazquez, Julio, Champac, Victor, Hawkins, Chuck, Segura, Jaume

Year:

2009

Language:

english

File:

PDF, 1.16 MB

english, 2009

24

[IEEE 2014 15th Latin American Test Workshop - LATW - Fortaleza, Brazil (2014.3.12-2014.3.15)] 2014 15th Latin American Test Workshop - LATW - Possibilities of defect-size magnification for testing resistive-opens in nanometer technologies

Garcia-Gervacio, Jose L., Martinez-Castillo, Jaime, Champac, Victor

Year:

2014

Language:

english

File:

PDF, 171 KB

english, 2014

25

Effectiveness of Low-Voltage Testing to Detect Interconnect Open Defects Under Process Variations

Moreno, Jesus, Renovell, Michel, Champac, Victor

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2015

Language:

english

File:

PDF, 772 KB

english, 2015

26

[IEEE 2010 First IEEE Latin American Symposium on Circuits and Systems (LASCAS) - Foz do Iguacu, Brazil (2010.2.24-2010.2.26)] 2010 First IEEE Latin American Symposium on Circuits and Systems (LASCAS) - A Short-channel silicon-based Split-Drain MAGFET measuring from 90 µT

Santillan-Quinonez, Gerard F., Champac, Victor, Murphy, Roberto S.

Year:

2010

Language:

english

File:

PDF, 1.19 MB

english, 2010

27

Exploiting magnetic sensing capabilities of Short Split-Drain MAGFETs

Gerard F. Santillan-Quiñonez, Victor Champac, Roberto S. Murphy

Journal:

Solid-State Electronics

Year:

2010

Language:

english

File:

PDF, 843 KB

english, 2010

28

Selection of Critical Paths for Reliable Frequency Scaling under BTI-Aging Considering Workload Uncertainty and Process Variations Effects

Gomez, Andres F., Champac, Victor

Journal:

ACM Transactions on Design Automation of Electronic Systems

Year:

2018

Language:

english

File:

PDF, 2.86 MB

english, 2018

29

Detectability Conditions of Full Opens in the Interconnections

Antonio Zenteno, Victor H. Champac, Joan Figueras

Journal:

Journal of Electronic Testing

Year:

2001

Language:

english

File:

PDF, 491 KB

english, 2001

30

Low VDD and body bias conditions for testing bridge defects in the presence of process variations

Villacorta, Hector, Garcia-Gervacio, Jose, Segura, Jaume, Champac, Victor

Journal:

Microelectronics Journal

Year:

2015

Language:

english

File:

PDF, 541 KB

english, 2015

31

Detectability Challenges of Bridge Defects in FinFET Based Logic Cells

Forero, Freddy, Galliere, Jean-Marc, Renovell, Michel, Champac, Victor

Journal:

Journal of Electronic Testing

Year:

2018

Language:

english

File:

PDF, 1.43 MB

english, 2018

32

Aging-Aware Power or Frequency Tuning With Predictive Fault Detection

Pachito, Jackson, Martins, Celestino V., Jacinto, Bruno, Semiao, Jorge, Vazquez, Julio C., Champac, Victor, Santos, Marcelino B., Teixeira, Isabel C., Teixeira, Joao Paulo

Journal:

IEEE Design & Test of Computers

Year:

2012

Language:

english

File:

PDF, 575 KB

english, 2012

33

[IEEE 2020 IEEE Latin American Test Symposium (LATS) - Maceio, Brazil (2020.3.30-2020.4.2)] 2020 IEEE Latin-American Test Symposium (LATS) - Analysis and detection of hard-to-detect full open defects in FinFET based SRAM cells

Perez, Z., Mesalles, Javier, Villacorta, H., Vargas, Fabian, Champac, Victor

Year:

2020

File:

PDF, 371 KB

2020

34

[IEEE 2010 15th IEEE European Test Symposium (ETS) - Praha, Czech Republic (2010.05.24-2010.05.28)] 2010 15th IEEE European Test Symposium - Computing the detection of Small Delay Defects caused by resistive opens of nanometer ICs

Garcia-Gervacio, Jose L., Champac, Victor

Year:

2010

Language:

english

File:

PDF, 405 KB

english, 2010

35

[IEEE 2009 10th Latin American Test Workshop - Rio de Janeiro, Brazil (2009.03.2-2009.03.5)] 2009 10th Latin American Test Workshop - A modern look at the CMOS stuck-open fault

Gomez, Roberto, Champac, Victor, Hawkins, Chuck, Segura, Jaume

Year:

2009

Language:

english

File:

PDF, 419 KB

english, 2009

36

[IEEE 2015 16th Latin-American Test Symposium (LATS) - Puerto Vallarta, Mexico (2015.3.25-2015.3.27)] 2015 16th Latin-American Test Symposium (LATS) - Message from the LATS2015 Chairs

Champac, Victor, Zorian, Yervant, Bolzani Pohls, Leticia, Agrawal, Vishwani

Year:

2015

Language:

english

File:

PDF, 98 KB

english, 2015

37

[IEEE 2012 IEEE 30th VLSI Test Symposium (VTS) - Maui, HI, USA (2012.04.23-2012.04.25)] 2012 IEEE 30th VLSI Test Symposium (VTS) - Small-delay defects detection under process variation using Inter-Path Correlation

Galarza-Medina, Francisco J., Garcia-Gervacio, Jose L., Champac, Victor, Orailoglu, Alex

Year:

2012

Language:

english

File:

PDF, 751 KB

english, 2012

38

Design-for-Test Techniques for Opens in Undetected Branches in CMOS Latches and Flip-Flops

Zenteno Ramirez, Antonio, Espinosa, Guillermo, Champac, Victor

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2007

Language:

english

File:

PDF, 684 KB

english, 2007

39

[IEEE 2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS) - College Station, TX, USA (2014.8.3-2014.8.6)] 2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS) - Analysis of fin height on FinFET SRAM cell hardening

Villacorta, Hector, Segura, Jaume, Bota, Sebastia, Champac, Victor

Year:

2014

Language:

english

File:

PDF, 1.07 MB

english, 2014

40

[IEEE 2015 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) - Daejeon, South Korea (2015.10.5-2015.10.7)] 2015 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) - A new sizing approach for lifetime improvement of nanoscale digital circuits due to BTI aging

Gomez, Andres, Champac, Victor

Year:

2015

Language:

english

File:

PDF, 1.04 MB

english, 2015

41

[IEEE 2019 IEEE European Test Symposium (ETS) - Baden-Baden, Germany (2019.5.27-2019.5.31)] 2019 IEEE European Test Symposium (ETS) - B-open: A New Defect in Nanometer Technologies due to SADP Process

Forero, Freddy, Renovell, Michel, Champac, Victor

Year:

2019

Language:

english

File:

PDF, 3.72 MB

english, 2019

42

Guest Editorial

Victor Champac, Ingrid Jansch Porto

Journal:

Journal of Electronic Testing

Year:

2003

Language:

english

File:

PDF, 26 KB

english, 2003

43

ECS Transactions [AAPM 25th Symposium on Microelectronics Technology and Devices - Sao Paulo, Brazil (September 6 - September 9, 2010)] - Equivalent Rectangular Active Region and SPICE Macro Model for Split-Drain MAGFETs

Santillan-Quiñonez, Gerard F., Murphy, Roberto S., Champac, Victor H., Pavanello, M., Claeys, C., Martino, J.

Year:

2010

Language:

english

File:

PDF, 343 KB

english, 2010

44

[IEEE 2016 IEEE East-West Design & Test Symposium (EWDTS) - Yerevan, Armenia (2016.10.14-2016.10.17)] 2016 IEEE East-West Design & Test Symposium (EWDTS) - Critical path selection under NBTI/PBTI aging for adaptive frequency tuning

Gomez, Andres F., Champac, Victor

Year:

2016

Language:

english

File:

PDF, 301 KB

english, 2016

45

[Frontiers in Electronic Testing] Timing Performance of Nanometer Digital Circuits Under Process Variations Volume 39 ||

Champac, Victor, Garcia Gervacio, Jose

Year:

2018

Language:

english

File:

PDF, 13.42 MB

english, 2018

46

Computing the Detection Probability for Small Delay Defects of Nanometer ICs

José L. García-Gervacio, Victor Champac

Journal:

Journal of Electronic Testing

Year:

2011

Language:

english

File:

PDF, 562 KB

english, 2011

47

[IEEE 2015 IEEE 33rd VLSI Test Symposium (VTS) - Napa, CA, USA (2015.4.27-2015.4.29)] 2015 IEEE 33rd VLSI Test Symposium (VTS) - An early prediction methodology for aging sensor insertion to assure safe circuit operation due to NBTI aging

Gomez, Andres, Poehls, Leticia, Vargas, Fabian, Champac, Victor

Year:

2015

Language:

english

File:

PDF, 1.18 MB

english, 2015

48

[IEEE 2015 16th Latin-American Test Symposium (LATS) - Puerto Vallarta, Mexico (2015.3.25-2015.3.27)] 2015 16th Latin-American Test Symposium (LATS) - Effective selection of favorable gates in BTI-critical paths to enhance circuit reliability

Gomez, Andres, Champac, Victor

Year:

2015

Language:

english

File:

PDF, 596 KB

english, 2015

49

Reliability Analysis of Small-Delay Defects Due to Via Narrowing in Signal Paths

Villacorta, Hector, Hawkins, Chuck, Champac, Victor, Segura, Jaume, Gomez, Roberto

Journal:

IEEE Design and Test

Year:

2013

Language:

english

File:

PDF, 952 KB

english, 2013

50

[Frontiers in Electronic Testing] Timing Performance of Nanometer Digital Circuits Under Process Variations Volume 39 || Mathematical Fundamentals

Champac, Victor, Garcia Gervacio, Jose

Year:

2018

Language:

english

File:

PDF, 875 KB

english, 2018

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